Digital engineering

4 to 1 Multiplexer (MUX) Work, Truth Table and Applications


A 4 to 1 Multiplexer is a composite circuit with a maximum of 22 input data; where ‘2’ is a select line. One of these data inputs will be connected to the output with the select lines. Since there are ‘n’ selection lines, there will be about 2n  combinations of “1” and “0”. 4 to 1 Multiplexer is also known as 4 to 1 MUX circuit.

In this tutorial, we are going to steady about behavior of 4 to 1 multiplexer. In pervious lecture we already learn about multiplexer, working and its truth table. The multiplexer is a combinational circuit and it is a memory less circuit. It means the present input does not depend on the past input.

What is Multiplexing?

Multiplexing is the process of combinations one or more signals and transmitting through a common channel. In analogue communication systems, a communication channel is a most valuable part, which should be used appropriately. To use the channel in an inexpensive and effective way, the concept of Multiplexing is very useful as it allows multiple users to share a single channel in a logical way.
The three most common types of Multiplexing methods are:

  • Time
  • Usually
  • Space

Two excellent examples of Multiplexing Systems used in our daily lives are the home phone network and Cable TV. Multiplexers are familiar in both Analog signal and Digital signals. Let’s focus on digital signals in this study, to keep things simple. The multiplexer is a widely used combination circuit and is an important building block for many digital systems.

These are widely used to build the chosen route between multiple sources and one destination. The basic multiplexer has various data input lines and one outgoing line. The application of multiplexer in digital circuit is data selection and data routes, digital calculators with multiplex indicators, telephone network, communication systems, waveform generators, etc.

What is a Multiplexer?

Multiplexer is a combination circuit. It has a 2n 2inputs lien and a single output line. In other word the multiplexer is a multiple inputs and one output. The binary information is place on the input line and directed to output line. The output line selection is depending on the select line.
Unlike encoder and decoder, there are “n” inputs lines and “m” input lines. The multiplexer is also treated as a MUX.


Generally the number of input lines depends  on the power of two such as 2, 4, 8, 16, etc. some of the most commonly usable multiplexer is  2 to 1, 4 to 1, 8 to 1 and 16 to 1 multiplexers.
Multiplexer is also available in IC forms various input and select line configurations. Some multiplexer ICs are listed below.

  1. 74157 = Quad 2-to-1 multiplexer
  2. 8158 = Quad 2-to-1 multiplexer
  3. 74153 = 4-to-1 multiplexer
  4. 74152 = 8-to-1 multiplexer
  5. 74150 = 16-to-1 multiplexer.

4 to 1 Multiplexer

A 4 to 1 MUX contains “FOUR” input lines and these are D0 D1 D2 and D3, two selected lines S0 and S1 and one output Y-line. Selected lines S0 and S1 select one of the four input lines to connect the outgoing line. The figure below shows a 4 to 1 MUX block diagram where, the multiplexer determines the input by the selected line.

Block diagram of 4 to 1 multiplexer

Below the figure show the block diagram of 4 to 1 MUX. In this type of multiplexer only have four inputs and one output line and to select lines.


4 to 1 multiplexer circuit diagram

The logical diagram of 4 to 1 MUX is shown below. In this logic diagram the output is ORed of four ANDed gate. Which are clearly shown in figure.


Below the given truth table of 4 to 1 multiplexer, in this type  of MUX have four  different inputs combinations 00, 10, 01 and 11 and two select lines switches the inputs A0, A2, D1 and A3 to the output respectively. The truth table the 4 to 1 multiplexer output configurations.

4 to 1 multiplexer truth table

S0 S1 A0 A1 A2 A3 Y (OUTPUT)
0 0 0 X X X 0
0 0 1 X X X 1
0 1 X 0 X X 0
0 1 X 1 X X 1
1 0 X X 0 X 0
1 0 X X 1 X 1
1 1 X X X 0 0
1 1 X X X 1 1


From the above truth table we can easily derive the output expressions as follows:
Y=S1‘ S0‘ A0+S1‘ S0 A1+S1 S0‘ A2+S1 S0 A3

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