D flip flop are also known as a “Delay flip flop” or “Data flip flop”. D flip flop can only store “1” bit binary data. It is advance version of “SET” and “RESET” flip flop with the addition of an inverter to prevent the “SET” and “RESET” from being at the same logic level. It is one of the widely use flip flop in digital electronics. It is mostly use in memory element in digital system. D flip flop also consider as a delay line element and Zero – Order Hold elements.
The D flip flop has two input line one is clock (CLK) and other is data (D) input, it has two outputs one output which is Q and the other is complement of Q represented by Q’. D flip flop symbol is given below.
D-type Flip-Flop Circuit
We know the SR flip flop has two inputs one is “SET” and other input is “RESET” and output is complement with each other. The D FF is made by connecting NOT gate to the input of SR flip flop. The S input is like as D input and R input is like an inverse of D input. Hence a D FF is similar to the SR flip flop in term complement of each others. The D flip flop is resolve drawback of race around in SR flip flop. The circuit diagram of SR flip flop is shown below.
Truth Table for the D-type Flip Flop
| CLK | D | Q | Q | Description |
| ↓ – 0 | X | Q | Q | Memory no change |
| ↑ – 1 | 0 | 0 | 1 | Reset Q – 0 |
| ↑ – 1 | 1 | 1 | 0 | Set Q – 1 |
↓ & ↑ denotes direction of clock pulse. It is assumed D FF flops are edge triggered flip flops.
D flip flop Types
- Synchronous D FF
- Asynchronous D FF
- Level Triggered D FF
- Edge triggered D FF
Master Slave D flip flops
The master slave D FF is design to avoid race around conditions, the other name of master slave flip flop is pulse triggered flip flops because the response time is equal to width of the one clock pulse.
The configuration of master slave FFs is 2- D flip flops one is master and other is slave, each are connected to a CLK pulse which is complementary with each other. When clock pulse is high master operate and slave in the hold condition, whereas when clock is low the slave is operate and master in hold position. The master output is input of slave.
74LS74 Dual D-type Flip Flops
Other Popular D-type flip-flops ICs
| Device Number | Device Description | Subfamily |
| 74LS74 | Dual D Flip Flops with Preset and Clear | LS TTL |
| 74LS175 | Quad D FlF with Clear | LS TTL |
| 74LS273 | Octal D FF with Clear | LS TTL |
| 4013B | Dual D FF | Standard CMOS |
| 40174B | Hex D FF with Master Reset | Standard CMOS |
IC Package:
The IC HEF4013BP is a Dual D-type flip-flops. It contain two D flip flops with 14 pin package. Below the figure show HEF4013BP IC and pin description.
Pin details
- Q- True output
- Q’ – Compliment Output
- CP – Clock Input
- CD – CLEAR-Direct input
- D – Data input
- SD – PRESET-Direct input
- VSS – Ground
- VDD – Supply voltage
Components Required:
- 1 No – IC HEF4013BP (Dual D flip-flops)
- LM7805
- Tactile Switch
- 9V battery
- LED (Green-1, Red 1)
- Resistors (1kὨ – 4, 220kὨ -2)
- Breadboard
- Connecting wires
D Flip-Flops Circuit Diagram and Explanation:
Applications of D Flip Flops
Now a day, D flips flop is use in many applications, like memory, frequency division, counter and many more. The various application of D flip flops is given below.
D type Flip Flops for Frequency Division
The D FF is use in frequency division. If output “Q” directly to the input making close loop feedback. It divides frequency by 2. That is the output is half of the input frequency.
Divide-by-2 Counter
The above diagram shows the D FF with close loop feedback which divide the input frequency by 2. And also show the graph of frequency division
Transparent Data Latch
The data latch is use in computer and electronic device. The design of data latch in such a way to have very high impedance at both the outputs Q and its inverse Q’. it reduce the impedance effect on the connecting circuit. For example it is use as a bi-directional, buffer, and bus driver and display driver.
4 – bit Data Latch
