Different Types of Shift Registers and its Applications with operations
Shift register is a combination of flip flop only single bit of binary data i.e. 0 or 1. We need flip flop to store the multiple bits of binary data. Single flip flops are use to store only one bit of binary data. For store of “n” number of binary data we need an “n” number of flip flops because flip flop can only one bit of binary data. Flip flop are use to store information and construction of register r. The shift register is a device which is the group of flip flop for store of binary data. Example, if a computer is to store 16 bit binary data, it uses 16 flip flops. Register input or output may be serial and parallel, it is based on requirement. The binary data bits series store by register is called “Byte” or “word”. The bit length of Byte is 8 bit and length of word is 16 bits (or 2 Bytes).
When number of flip flop connects in series, it is called register. The store information transferred within register is called as ‘shift register’. It is a sequential logic circuit that can be used for the storage or the transfer of binary data on ever clock cycle.
What is Shift Register:
Shift register are the counter and form of sequential logic circuit. The sequential logic circuit only affected by the present input but also previous history, it is opposite of the combination logic circuit.
It is a sequential logic circuit that can be used for the storage or transfer of binary data. This sequential circuit load data present on input and it move or shift to the output when clock pulse arrive hence it is called shift register.
Register are used for store information or movement of data. It commonly used in computer and calculator to store data, or convert the data either serial to parallel or parallel to serial format. Shift register ICs are generally have a clear or reset connection so that they can be set or reset. The shift register operate in four different modes;
- Serial-in to Parallel-out (SIPO) – The binary data loaded in serial, one bit at a time and the parallel data is available at the output side.
- Serial-in to Serial-out (SISO) – In this mode the data is serially shifted “IN” and “OUT” the data is shifted serially “IN” and “OUT” of the register, one bit at an every clock pulse in either a left or right.
- Parallel-in to Serial-out (PISO) – Parallel binary data is loaded into the register and the data shifted out of the serially at every clock signal.
- Parallel-in to Parallel-out (PIPO) – Parallel binary data is loaded into the register and the data shifted out of the parallel at every clock signal.
The movement of data from left to right in shift register is shown below:
Serial-in to Parallel-out (SIPO) Shift Register
4-bit Serial-in to Parallel-out Shift Register
It is a serial input and parallel output and commonly known as SIPO shift register. This type of register is use for conversion of data from serial to parallel. Let assume that all flip flop are RESET (clear input) position and the out of QA to QD are at “0” logic level it means no parallel output data.
When we apply logic “1” data input of the flip flop and the first clock pulse are arrive than the output FFA output QA will be set HIGH to logic “1”. The all other output of flip flop still remains same “0”. Assume the FFA again return to LOW “0” giving us one data pulse or 0-1-0.
The second clock pulse are arrive and the output of FFA will change to logic “0” and the FFB output QB HIGH to logic “1” as input D has “1” on it from QA. The logic “1” has been “shifted” along the register to the right as it is now at QA.
The third clock pulse arrive the logic “1” moves to the output FFC ( QC ) and show on until arrive of fifth clock pulse which sets all the outputs QA to QD become to logic level “0” because the input to FFA has logic level “0”.
As we seen the each clock pulse arrive, the logic “1” value moves or shifted right, and it is shown in table until the complete value of 0-0-0-1 is store in register. This value can read directly from the outputs of QA to QD.
The flowing process converts the data from serial to parallel. The following truth table and waveforms are shown below.
Data shifting through a Shift Register
| Clock Pulse No | QA | QB | QC | QD |
| 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 |
| 2 | 0 | 1 | 0 | 0 |
| 3 | 0 | 0 | 1 | 0 |
| 4 | 0 | 0 | 0 | 1 |
Serial-in to serial-out shift register
This shift register is similar to the shift-in parallel-out register, except the data was directly read in parallel form from output Q0 to Q2. In serial in to serial out is allowed to flow straight through register and out of the other end serially. Since it has only one input and one output port, the shifting of DATA in shift register one by one at a time in serially hence it is called serial in to serial out shift register or SISO. It is one of the simplest register in which have three flip flop, it has only two connection with the flip flop and one common clock pulse of all flip flop. In SISO register the DATA enters the left hand side of flip flop and the serial out taken from the right hand of flip flop and the sequencing clock signal (CLk). Ever clock pulse signal the data shifts to the next stage of flip flop. The logic diagram is shown below.
Working principle of 3-bit SISO shift register
Let us assume the DATA bit “011” sending in shift register in input.
Initially the status of D flip flop is low level Q0 Q1 Q2 =000. Now understand the operation of 3- bit serial in to serial out for the following table which are give below:
| No of positive edge of Clock | Serial Input | Q2 | Q1 | Q0 |
| 0 | – | 0 | 0 | 0 |
| 1 | 1 LSB | 1 | 0 | 0 |
| 2 | 1 | 1 | 1 | 0 |
| 3 | 0 MSB | 0 | 1 | 1 LSB |
| 4 | – | – | 0 | 1 |
| 5 | – | – | – | 0 MSB |
Initially the all flip flop is zero level in the absence of clock signal Q0 Q1 Q2 =000. Here the serial output receive form the Q0, the LSB DATA bit received “1″ at 3rd clock signal and the MSB DATA bit received 5th of the positive edge clock pulse. Therefore, the 3 DATA bit required 5 positive edge clock pulses for produce a valid output. Similarly, the “N” DATA bit SISO shift register requires 2N-1 positive edge clock pulses signal in order to shift ‘N’ bit information.
Parallel-in to Serial-out (PISO) Shift Register
The parallel in to serial out is exactly opposite of the serial in to parallel out. In parallel in to serial out shift register the input is loaded into the register in the parallel form and the output is taken out from the right side of the flip flop. The input pin PA PB PC PD and single output “Q”. The DATA output is taken out serially on each clock pulse. In this type of register not required the four clock pulse to load in flip flop but it required four clock pulses to unload the DATA at output side. It is convent the parallel data into serial data format.
4-bit Parallel-in to Serial-out Shift Register
It is used to multiplex various DATA input to a single serial DATA output line for directly transfer of DATA in computer or communication system. IC 74HC166 is the 8 bit PISO shift register.
Working principle of 3-bit PISO shift register
The parallel in to serial out is revere of the serial in to parallel out. It has three parallel input lines and only single output line. The block diagram and working principle is shown below:
Assume that it has three D-type flip flop are cascaded, it has three input line from D0 to D2 and only one output Q0, the working of 3 DATA bit parallel in to serial out shift register by applying binary data “011” in parallel formats. Initially the flip flop is low level, when the clock pulse is applied all binary DATA lodes in flip flop and every clock plus we get out “011”.
Truth table of 3 bit PISO shift register is shown below:
| No of positive edge of Clock | Q2 | Q1 | Q0 |
| 0 | 0 | 1 | 1 LSB |
| 1 | – | 0 | 1 |
| 2 | – | – | 0 LSB |
We receive the serial output from Q0 we received the LSB bit “1” and MSB “0” at three positive edge trigger clock pulse. The N-bit shift registers required N-1 positive edge clock pulse for obtaining N-bit original information.
Parallel-in to Parallel-out (PIPO) Shift Register
The type of register are use for temporary storage or a time delay device, it is similar to the serial in to serial out SISO shift register configuration. In PIPO shift register the DATA in and out in parallel formats. The DATA inputs from PA to PD and DATA outputs from QA to QD. In PIPO shift register it need only one clock signal for uploading DATA input and unloading output. The block diagram of 4-bit PIPO is shown below:
4-bit Parallel-in to Parallel-out Shift Register
Universal Shift Register
The universal shift register perform the serial to serial, serial to parallel, parallel to serial and parallel to parallel operation, hence it is called universal shift register. It is available in TTL and CMOS IC’s. TTL IC’s number 74LS194, 74LS195 or the CMOS IC’s number 4035.
4-bit Universal Shift Register 74LS194
Applications of shift Registers
- Shift register used for temporary register for information storage.
- It is use for transfer of DATA and DATA manipulation
- Produce time delay in digital circuit through serial-in to serial-out and parallel-in to parallel-out.
- Serial-in to parallel-out to convert DATA in parallel formats output DATA.
- Parallel-in to serial-out to convert DATA in serial formats output DATA.
- It is use in communication line and demultiplexing of DATA.
Also read:- Combinational circuit, Multiplexer
