flip flop

SR Flip Flop- Circuit, Truth Table, Working and Gates implementation


SR Flip Flop- Circuit, Truth Table and Working

The example of combinational circuit is the Multiplexers, Demultiplexes, Encoders, Decoders, Parity Generators and Checkers. These circuit is memory less and no feedback element. The combinational circuit output is only depends on the present input not depends on the past input. You can visit the combinational circuit tutorial. On the other side the output is not depends on the only present input but also depends on the past input. This type of circuit is called sequential circuit. The sequential circuit has memory element, feedback line, control line and the output of sequential output is depends on the present past input. The sequential circuit has memory that store data for later use. The circuit or device able to store data and act as a memory unit are called flip flop or latched. The flip flop can only store only one bit of binary data.

NOTE: The terms “latch” and “flip-flop” will be used synonymously, although technically they are slightly different. To put the difference in simple terms, a flip-flop is a clock-controlled latch i.e., the output changes only when there is a clock signal (a HIGH or LOW level, depending on the design).

What is a Flip-Flop?

A flip flop is a basic memory element of digital electronics which can only store only one binary bit. The one binary bit may be “ZERO” and “ONE”. A flip flop has Bastable element, it means the output of flip flop will be change when clock pulse is applied.

A simple flip flop can be design by using to inverter connected in series with a feedback from output of second inverter to the input of first inverter. Below the figure shows flip flop using inverter.


Let the Q1 is the input and Q3 is the output of first inverter and second inverter respectively. Below the figure the feedback are disconnected and if Q1= 0 by connecting to ground the output is Q3 = 0. Now feedback is connected by disconnecting Q1 to ground terminal, the Q3 will still continue to be at 0.


This process will be also same for logic high “1”


The flip flop has two stable state until the output will not change when eternal clock pulse are not applied.

SR Flip-flop

The SR flip flop is also known as SR latch is one of the basic sequential logic circuit types of flip flop. It has two input “S” and “R” and two output Q and Q’. If Q is “1” the latch is said to be SET and if Q is 0 the latch is said to be RESET. The design of SR flip flop by cross coupled “NAND” gates or “NOR” gate.

When the device is “SET” means output is “1” , and is labelled S  and when the output is “RESET” means the output is “0”, labelled R. the SR stands for “Set-Reset”. The reset input reset the flip flop to its original state with an output Q that will be either “1” or “0” logic depending upon the set/reset condition.

The NAND logic gate SR flip flop has a feedback path from both of its outputs back to its opposite inputs, it use for store one bit information. Set, Reset and its current output Q relating to its current state are the three inputs of SR flip flops. The term of flip flops means “flipped” into one logic Set state or “flopped” back into the original logic Reset state.

NAND Gate SR Flip-Flop

The simplest way to design single bit set-reset flip flops is cross coupled 2 input NAND gates as shown in figure. The set reset bistable is also called active low SR NAND Gate Latch, so that there is feedback from each output to one of the other NAND gate inputs. The circuit consist of SET and RESET terminal input with two corresponding outputs Q and its inverse or complement Q (not-Q) as shown below.

 Basic SR Flip-flop


  1. Set State

The circuit shows above is SR flip flops. If the input RESET is “0” and other input SET is “1” than the circuit is called SET condition. For output “1”, one of the input of NAND gate Y  has logic “0” for Q’ is “1”. The output Q’ is feed to NAND A, both input is one the output Q=0

If the reset input is “1” and set remain high, NAND gate Y inputs are now R = “1” and B = “0”. Since, one input is still at logic “0” the output at Q’ still remains HIGH and there is no change of state. Therefore, the flip-flops circuit is said to be “Latched” or “Set” with Q’ = “1” and Q = “0”.

  1. Reset state

In second state Q’ is logic “0” not Q=1 and reset is “1” and set is “0”, As NAND gate X has one of its input is logic zero for Q =1. Again the output Q is feedback to NAND gate Y input therefore, Q’ = “0”.

If the set input is become logic “1” with input remaining at logic “1” the output Q still remain LOW at logic level “0” and there is no change of state. We can define this “set/reset” action in the following truth table.

Truth Table for this Set-Reset Function

State S R Q Q Description
Set 1 0 0 1 Set Q » 1
1 1 0 1 no change
Reset 0 1 1 0 Reset Q » 0
1 1 1 0 no change
Invalid 0 0 1 1 Invalid Condition


It can be seen that when both set and reset input is “1” the output Q and Q’ can be either “0” or “1” depending upon the pervious state. Therefore the S=R=1 does not change the output. However the S=R=0, at this condition the set reset flip flops is Invalid Condition

 S-R Flip-flop Switching Diagram


NOR Gate SR Flip Flop

The circuit diagram using NOR gate shown below.


The cross connection of NOR gate to made SR flip flop. The working of NOR gate is similar to NAND gate SR.

Truth table of  using NOR gate is shown below:

0 0 No Change No Change
0 1 0 1
1 0 1 0
1 1 0 0


Quad SR Bastable Latch 74LS279


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