The XOR gate is very useful circuit in many type of combinational circuit. In this tutorial we will discuss about XOR gate. The XOR gate are also known as EX-OR gate or Exclusive-OR gate. It is not frequently use as OR gate, it has own significance. In previous tutorial we all ready discuss the AND gate and OR gate. In this tutorial we discuss the truth table, symbol and implementation of XOR gate. In XOR gate the output will be Q=1 when only A= “1” or B= “1” but not together at same time. When binary inputs “01” or “10” than the output will be “1”. This is known as XOR gate.
In other word the XOR output will “HIGH” when both inputs are “DIFFRENT” with respect to each other. The Boolean expression of: Q = (A ⊕ B) = A’B + AB’.
Introduction to XOR Gate
XOR gate is an important circuit use in digital electronic. It is also known as EX-OR gate or Exclusive-OR gate, which implement an exclusive or logic. When the output of XOR gate is “HIGH” its inputs will be different with each other. It is formed by combinations of standard logic gates that are mostly used in building arithmetic logic circuits, error detection circuits, computational logic and comparators.
XOR Symbol
There are multiple standers for defending the electronics component. Generally we use the Institute of Electrical and Electronics Engineers-IEEE and International Electrotechnical Commission-IEC standards and standards are shown below.
It is a Hybrid logic gate. The Boolean expression of output of XOR gate is a combining of addition, Multiplication and inverting of inputs. We obtain the Boolean expression by Karnaugh Maps or K – Maps along with the truth table.
XOR Truth Table
The XOR gate truth table is given below. In this truth table the output will be “LOW” when both inputs are same and the output is “HIGH” when both inputs are different.
Inputs | Output | |
A | B | Q |
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 0 |
This truth table is use in K-map representation of the XOR Gate which is shown below.
XOR Boolean Expression
Using the above K-Map, we can now derive the Boolean Expression for XOR Gate. If A and B are two inputs of the XOR gate, its output is given as:
Q = A’ B + A’ B
The XOR output is represented as:
Q = A ⊕ B
It can also be written as:
Q = (A + B) (A’ + B’)
Applying De Morgan’s law above Boolean expression, we get:
Q = (A + B) (A B)’
Digital Logic “XOR” Gate
2-input XOR Gate
Symbol | Truth Table | ||
2-input XOR Gate |
B | A | Q |
0 | 0 | 0 | |
0 | 1 | 1 | |
1 | 0 | 1 | |
1 | 1 | 0 | |
Boolean Expression Q = A ⊕ B | A OR B but NOT BOTH gives Q |
The Boolean expression of XOR gate is Q = A’ B + A’ B
The truth table shown above that the output goes “HIGH” when the both inputs are “DIFFRENT” with each other and when the both inputs are same at a same time output will be “LOW”. Due to this reason the XOR logic gate to compare the inputs and produce an output value. It is mostly use in computational logic circuits. Then an XOR function with more than two inputs is called an “odd function” or modulo-2-sum (Mod-2-SUM),
3-input Ex-OR Gate
Symbol | Truth Table | |||
3-input Ex-OR Gate |
C | B | A | Q |
0 | 0 | 0 | 0 | |
0 | 0 | 1 | 1 | |
0 | 1 | 0 | 1 | |
0 | 1 | 1 | 0 | |
1 | 0 | 0 | 1 | |
1 | 0 | 1 | 0 | |
1 | 1 | 0 | 0 | |
1 | 1 | 1 | 1 | |
Boolean Expression Q = A ⊕ B ⊕ C | “Any ODD Number of Inputs” gives Q |
Boolean expression of three inputs XOR logic is:
Q = AB’C’ + A’BC’ + A’B’C + ABC
In three inputs XOR logic is slightly different to the slandered XOR logic, because it has three inputs. The Boolean expression of the given logic is AB’C’ + A’BC’ + A’B’C + ABC. The symbol described this logic logic is a plus sign, ( + ) within a circle ( Ο ), and the resulting symbol for an this logic function being given as: ( ⊕ ). We already said this logic is not exactly same the basic logic, it is a combination of basic logic connected together to produce a XOR logic. Using truth table of two inputs, we can expand the XOR logic(A+B).(A.B)’ this means we can easily express the XOR gate using other logic.
XOR Gate Equivalent Circuit
The above figure shows the equivalent circuit of XOR gate using OR logic NAND logic and AND logic the outputs of OR and NAND logic goes to the input of AND logic. It is the easier way to produce the XOR logic.
XOR Function Realization using NAND gates
The above figure shows the XOR Function using four NAND gates, it perform the adder and half adder asthmatic operations as they can provide a “carry-bit” function or as a controlled inverter,
The Boolean expression of XOR gate using NAND gate is:
Q = A’ B + A B’
Q = A’ B + A B’ + A A’ + B B’
Q = (A + B) (A’ + B’)
Applying de Morgan’s Law on above equation, we get:
Q = (A + B) (A B)’
We implement NAND gates circuit.
Q =A (AB)’ + B (AB)’
Taking complement on both sides, we get:
Q’ = (A (A B)’ + B (A B))’
Q = (A (A B)’)’ (B (A B)’)’ = (A (AB)’)’ (B (AB)’)’
Again, apply complement on both sides.
Q = {(A (A B)’)’ (B (A B)’)’}’= ((A (AB)’)’ (B (AB)’)’)’
This equation looks like a NAND Gates.
Commonly Available TTL and CMOS XOR logic gate IC’s
Here is the some Following list commonly available XOR ICs.
IC Number | Description |
4030 | Quad 2-Input XOR logic Gates |
4070 | Quad 2-Input XOR logic Gates |
7486 | Quad 2-Input XOR logic Gates |
74LS86 | Quad 2-Input XOR logic Gates |
741G86 | Single 2-input XOR logic |
74136 | Quad 2-Input XOR Gates with Open Collector Outputs |
74386 | Quad 2-Input XOR logic Gates |
7486 Quad 2-Input Exclusive-OR Gate IC
The Ex-OR gate ic 7486 is the Quad with 2 inputs logic. In this single package IC has four XOR. The detail of pin diagram and pin description is given below.
Pin Number | Description |
1 | Gate 1 Input A |
2 | Gate 1 Input B |
3 | Gate 1 Output Y |
4 | Gate 2 Input A |
5 | Gate 2 Input B |
6 | Gate 2 Output Y |
7 | Ground |
8 | Gate 3 Output Y |
9 | Gate 3 Input A |
10 | Gate 3 Input B |
11 | Gate 4 Output Y |
12 | Gate 4 Input A |
13 | Gate 4 Input B |
14 | Positive Supply |
Applications of XOR Gate
There are many application of Ex-OR logic gate. Some applications are given below:
Used in Adder (Addition)
This logic gate are use in half adder, it design for addition of single bit adder which is called half adder. It add two bit and produce one single output. The logic diagram is shown below.
For example the binary addition of two bit “1” and “1” the output of addition is “10” and in decimal it is “2”. For example, if we add two bits ‘1’ and ‘1’ in binary addition, we get the answer ’10’ and in decimal addition method we get 2. For n bit adder can produce by cascade of many single bit adder to calculate the longer binary addition.
Pseudo-Random Number Generation
The pseudo random number generators are also known as liner shift registers. For generation of random number we are cascade the XOR gate in specified format for producing the liner feedback shift register.